1. Field of the Invention
This invention relates in general to telecommunication systems of the type employing pulse code modulation and wherein switching is accomplished on a time division multiplex basis. More particularly the present invention is drawn to a technique wherein 3-way communications are accomplished by means of a single cycle of memory access wherein all operations are performed in parallel simultaneously in time thus substantially increasing time switch capacity.
2. Description of the Prior Art
In telecommunication systems wherein switching is accomplished on a time division multiplex basis, the information memory is normally scanned at an 8 Khz rate (this being the same sampling as the voice sampling rate) and for each port having access thereto the included random access memories are accessed three times. Thus, as the number of parts is increased, the cycle times for random access memory access becomes smaller, limiting the ultimate capacity of such time switches.
In a conventional approach for an all time non-blocking time switch, wherein the dwell time per port and the number of access per port is fixed, memory access time specified determines the maximum number of ports. Thus when a large number of ports is to be accommodated faster memories are required and faster associated peripheral circuitry. With a given memory specification, more ports than the ultimate capacity may be accommodated by duplicating the network in blocks of the ultimate size. Since each block operates independently in parallel the amount of memory required increases approximately as the square of the number of blocks operating in parallel. If the three cycles of operation could be combined into one using additional information memory only, then the time switch capacity could be increased threefold using the same memories and the same dwell time per port. In this particular approach the amount of hardware is almost linear as opposed to almost square growth with the previously outlined approach.
In the past various systems have been developed with the purpose of combining several cycles of operation into one for the purposes outlined above. U.S. Pat. No. 3,046,348 to Osborn discloses a memory system utilized in a telephone system wherein read and write operations are both carried out within the same time period. In the arrangement disclosed a time slot is divided into two portions. The first portion is used to readout the memory while the second portion is used to write in the memory. While read and write occur within the same period, they do not occur simultaneously, neither does the disclosed arrangement provide for conferencing.
In U.S. Pat. No. 3,740,482 to Plank et al., a time division telephone system is disclosed which sequentially samples messages transmitted between two central offices. In the arrangement taught, transmission of messages is parallel because messages are sampled along a plurality of buses and a plurality of switching devices are each operatively related to a separate sample storage means in the transmitting station into one of the buses. Again simultaneous read and write with its attendant advantages is not disclosed.
U.S. Pat. No. 3,632,883 to Aagaard discloses a time division multiplex telecommunication exchange wherein information from all the channels is sequentially stored in a memory along with the code numbers. At a time determined by the address and output channel, the address and input channel is introduced into a second register. The output of the second register is decoded and used to switch the output of the first register so as to read the contents of the first register. However, the entering of the information into the register and the switching of the output of the register do not occur simultaneously. Aagaard also does not provide any provision for three way conferencing.
Accordingly it is the purpose of the present invention to describe a technique for use in time division multiplex switching systems whereby three consecutive cycles of memory access per port are reduced to a single cycle by performing all operations simultaneously so that the switch time capacity in a pulse code modulated time switch can be increased.